Co-ordinate addressing of liquid crystal cells

ABSTRACT

A co-ordinate addressed bistable liquid crystal cell is switchable between its two stable states by oppositely directed electric potential differences applied across the liquid crystal layer thickness between a front-plane electrode and the members of a co-ordinate address array of electrode pads of an active back-plane. Refresh data is compared with currently displayed data so that only those pixels scheduled for switching are subjected to switching stimuli. The electrode pad of a pixel scheduled for switching is taken from the potential of the front-plane electrode to a different potential by connection to a voltage source. It is then electrically isolated from that voltage source for a further period before its potential is restored to that of the front-plane electrode. This enables rows of pixels to be addressed with a line address time considerably shorter than the time necessary to effect full switching.

This invention relates to the co-ordinate addressing of liquid crystalcells. Co-ordinate addressing of such cells can be achieved by methodsin which each pixel is defined as the area of overlap between one memberof a set of row electrodes on one side of the liquid crystal layer andone member of another set of column electrodes on the other side. In analternative co-ordinate addressing method the liquid crystal is backedby `an active back-plane ` which has a co-ordinate array of electrodepads which are addressed on a co-ordinate basis within the activeback-plane, and electrical stimuli are applied to the liquid crystallayer between individual members of this set of electrode pads on oneside of the liquid crystal layer and a co-operating front-planeelectrode on the other side of the liquid crystal layer. Generally thefront-plane electrode is a single electrode, but in some instances itmay be subdivided into a number of electrically distinct regions. Theactive back-plane may be constructed as an integrated single crystalsemiconductor structure, for instance of silicon.

This invention relates in particular to the active back-plane addressingof liquid crystal cells whose response to an electrical stimulus issensitive to the polarity of that stimulus.

In the electrical addressing of liquid crystal cells it is generallyimportant to ensure that no pixels are subject to any significant longterm cumulative charge imbalance that could give rise to electrolyticdegradation effects within the cell. In the cases of cells whoseresponse is not polarity sensitive, long-term charge balance can oftenbe ensured by using charge-balanced a.c. stimuli throughout, but clearlythere are problems in transferring this approach to the addressing ofcells whose response is polarisation sensitive because in thesecircumstances the application of a charge-balanced a.c. stimulus to apixel may make it make a temporary excursion from its initial state tosome other state, but is then likely to restore it once again to itsinitial state.

In the ensuing description any particular pixel of a co-ordinate arrayof pixels is identified by its row and column co-ordinates. Whereas inconventional usage of the terms `row` and `column`, rows and columns arerespectively identified as horizontally-extending andvertically-extending lines; in this instance these terms are employed ina wider sense that does not imply any particular orientation of the rowand column lines with respect to the horizontal, but merely that thesets of row and column lines intersect each other.

According to the present invention there is provided a method ofaddressing a liquid crystal cell having a co-ordinate array of pixels,wherein data for refreshing the cell is compared with the data existingprior to refresh to determine those pixels which require to have theirstates changed, and wherein those pixels are accessed by developing apositive, or negative, electric potential difference across thosepixels, according into which state they are to be changed, for apredetermined period of time before re-establishing a zero potentialdifference, whereby no pixel is consecutively accessed twice by the samepolarity of potential difference.

According to the present invention there is further provided a method ofcoordinate addressing a liquid crystal cell that includes a liquidcrystal layer which, by the application of oppositely directed electricpotential differences across the thickness of the layer, is enabled tobe switched between two stable states, which cell is switchable betweensaid two stable states using an active back-plane provided with aco-ordinate array of electrode pads on one side of the liquid crystallayer, which pads co-operate with a front-plane electrode on the otherside of the liquid crystal layer to define an associated co-ordinatearray of pixels within the liquid crystal layer, wherein data forrefreshing the cell is compared, pixel address by pixel address, withpre-existing data currently displayed by the pixels to determine whichpixels require to have their states changed, and wherein only thoseelectrode pads whose associated pixels are pixels that require to havetheir states changed are accessed taking their potential from apotential equal to that of the front-plane electrode to a differentpotential for a predetermined period before restoring it to its formerpotential equal to that of the front-plane electrode, the differentpotential being either a predetermined amount above the potential of thefront-plane electrode, or an equal amount below that potential.

By use of this method the potential maintained across any individualliquid crystal pixel is normally held at zero, and a non-zero potentialis only developed when the pixel needs switching from one state to theother. Under these circumstances it is subjected to a unidirectionalpotential of known magnitude for a known limited duration. Assumingcharge balance beforehand, this gives rise to a specific limited amountof charge imbalance but, because of the comparison process, it is neveraddressed twice consecutively in the same direction, and so it ispossible to arrange matters so that the charge imbalance is notcumulative. The comparison process performed in the back-plane ensuresthat the next addressing of this pixel is in the opposite direction, andso the charge imbalance, if any, existing after the second addressingcan be made equal to the charge imbalance, if, any, existing prior toits first addressing.

The invention also provides a back-plane co-ordinate addressed liquidcrystal device, which device includes a liquid crystal cell containing aliquid crystal layer switchable, by the application of oppositelydirected electric potential differences across the thickness of thelayer, between two stable states, which cell has an active back-planeprovided with a co-ordinate array of electrode pads on one side of theliquid crystal layer, which pads co-operate with a front-plane electrodeon the other side of the liquid crystal layer to define an associatedco-ordinate array of pixels within the liquid crystal layer, whichdevice also includes a data processor which is adapted to compare datafor refreshing the cell pixel address by pixel address with pre-existingdata currently displayed by the pixels to determine which pixels requireto have their states changed, and is adapted to refresh the cell bytaking the potential, only of those electrode pads whose associatedpixels are pixels that require to have their states changed, from apotential equal to that of the front-plane electrode to a differentpotential for a predetermined period before restoring it to its formerpotential equal to that of the front-plane electrode, the differentpotential being either a predetermined amount above the potential of thefront-plane electrode, or an equal amount below that potential.

There follows a description of back-plane co-ordinate addressed liquidcrystal devices and their method of operation embodying the invention inpreferred forms. The description refers to the accompanying drawings inwhich:

FIG. 1 is a block-diagram of a back-plane co-ordinate addressed liquidcrystal device.

FIG. 2 depicts a schematic cross-section of the liquid crystal cell ofthe device of FIG. 1,

FIG. 3 is a diagram of a pixel pad addressing arrangement,

FIG. 4 is a diagram of an alternative pixel pad addressing arrangementemploying an extra gate per pixel, and

FIGS. 5 and 6 are respectively diagrams of parts of the column and rowaddressing units of the device of FIG. 1.

Referring to FIG. 1, a data processor 10 receives incoming data over aninput line 11, and controls the operation of row and column addressingunits 12 and 13 which provide inputs on lines 14 and 15 to theelectrodes of a back-plane co-ordinate addressed liquid crystal cell 16with pixels arranged in a co-ordinate array of n rows and m columns. Inthis cell 16 a hermetic enclosure for a liquid crystal layer 20 (FIG. 2)is formed by securing a transparent front sheet 21 with a perimeter seal22 to a back sheet 23. Small transparent spheres (not shown) of uniformdiameter may be trapped between the two sheets 21 and 23 to maintain auniform separation, and hence uniform liquid crystal layer thickness. Onits inward facing surface, the front sheet 11 carries a transparentelectrode layer 24, the front-plane electrode layer, while a co-ordinatearray of pixel pad electrodes 25 are similarly carried on the inwardfacing surface of the back sheet 23. These two inward facing surfacesare treated to promote a particular molecular alignment of the liquidcrystal molecules in contact with these surfaces in the same direction.The back sheet 23 constitutes an active back-plane, by means of whichthe pixel pads 25 may be individually addressed on a row by row basis.Within its active structure, which may for instance be constructed insingle crystal silicon, it contains the row and column addressing 12 and13 units (FIG. 1), and may additionally contain the data processor 10.The area of overlap between the front-plane electrode layer 24 and anindividual pixel pad 25 defines a pixel of the cell. The liquid crystallayer 20 is composed of a ferroelectric chiral smectic C materialexhibiting long-term bistability when confined between the two majorsurfaces of its confining envelope. The thickness of the layer 20 isequal to an odd number of quarter wavelengths divided by thebirefringence of the liquid crystal material, and it is viewed through apolariser (not shown). An individual pixel can be switched into one ofthese two bistable states by the application of a potential differencebetween its pixel pad 25 and the front-plane electrode 24. If thedirection of that potential difference is reversed, the pixel isswitched into the other bistable state.

The application of a potential difference in one direction across thethickness of the chiral smectic C phase layer 20 will promote alignmentof the liquid crystal molecules in a direction inclined at an angle φwith respect to the parallel surface alignment directions, where φ isthe tilt angle of the chiral smectic phase. A reversal of the potentialdifference will change the promoted molecular alignment to the angle--φwith respect to the parallel surface alignment directions. However inmay instances some significant relaxation of alignment occurs uponremoval of the switching potentials. Since some considerable period oftime is liable to elapse between refreshings of any given pixel, such apixel will normally be observed in its fully relaxed state. It istherefore preferred to employ a cell in which those relaxation effectsare kept to a minimum. One such construction of cell in which theserelaxation effects are minimised is described in our co-pending Britishpatent application No. 9002105.6, to which attention is directed, inwhich surface alignment is provided by obliquely evaporated layers andthe cell is subsequently `conditioned` by the application of arelatively high potential difference across the thickness of its liquidcrystal layer.

In the case of the pixel pad addressing arrangement of FIG. 3, a singlegate 30 is associated with each pixel pad 25. All the gates of a row ofpixel pads are enabled by the application of a suitable potential to arow electrode 31 associated with that row. Enablement of this row ofgates serves to connect each pad with its associated column electrode32. Normally the column electrodes are maintained at the potential ofthe front-plane electrode 24 (FIG. 2) so that no potential difference isdeveloped across the pixel when its gate 30 is enabled. Under thesecircumstances the pixel will remain in its pre-existing state when thatparticular row of pixels is accessed by the enablement of the row ofassociated gates. If however a pixel requires to have its state changed,this is accomplished by applying a pulse to its associated columnelectrode during the enablement time slot.

Thus, while an enabling pulse 33 is applied on one of the column rowelectrodes 31, a pulse 34 applied on one of the electrode 32 lines willswitch the addressed pixel into one bistable state, whereas anequivalent oppositely directed pulse 35 would switch it to the otherbistable state. Pulses 34 and 35 terminate before the end of pulse 33 sothat the potential developed across the pixel to switch it is removedfrom the pixel before the pixel pad is once again isolated by thedisablement of its associated gate.

The pulses 34 and 35 have to be of long enough duration to cause thepixel to switch. The pulse 33 has to be even longer, because it mustadditionally give time for the potential to be removed from the pixelpad when a pulse 34 or 35 has terminated.

Normally the liquid crystal switching time is quite long compared withthe time required to charge up or discharge a pixel pad. Thus a drawbackof this approach is that the minimum line address time, the minimumduration of a pulse 33, is liable to be considerably longer than thetime necessary to charge up a pixel pad to its required potential.

This problem can be overcome by adopting the addressing arrangement ofFIG. 4, which involves the use of an extra gate 40 for each pixel pad,and the use of extra row and column electrodes 41 and 42. The columnelectrodes 42 are all maintained at the potential of the front-planeelectrode 24 (FIG. 2) so that, whenever a gate 40 is enabled, nopotential difference is developed across its associated pixel. The rowelectrodes 41 are normally maintained at a potential causing theirassociated gates to be sustained in their enabled states. When a row ofpixels is to be addressed, a pulse 43 is applied to the relevant pixelpad row electrode 41 to disable all the gates 40 of that row just beforethe commencement of the pulse 33 applied to the corresponding rowelectrode 31 that enables all the gates 30 of the row. Meanwhile thecolumn electrodes 32 have been connected on an individual basis by gates(not shown in FIG. 4) to any one of three voltage rails (not shown inFIG. 4). The second rail is maintained at the potential of thefront-plane electrode, while the first and third rails are maintained atpotentials respectively an equal amount above and below the front-planeelectrode potential. Thus a gate set to connect the column electrode 32to the first rail causes a potential to be applied to the relevant pixelpad tending to switch the pixel to one particular state. If set toconnect the column electrode 32 to the third rail, the gate would causea potential to be applied tending to switch the pixel to the otherstate; whereas, if set to connect the column electrode 32 to the secondrail, no potential would be developed across the pixel and hence itwould remain in its pre-existing state. Pulse 43 is of longer durationthan pulse 33 and so terminates after the termination of pulse 33. Whenthe pulse 33 terminates, the gates 30 of the addressed row resume theirdisabled states, and hence, neglecting leakage effects, the potentialsnow appearing on the individual pixel pads are sustained until thetermination of pulse 43. At this stage, gates 40 of the addressed roware once again enabled, and the potentials, if any, developed across theindividual pixels of the row are reduced to zero.

Incoming data with which the device is to be addressed is fed over line11 to the data processor 10, which compares the incoming datapixel-by-pixel with a record of the data currently being displayed bythe liquid crystal cell 16. A portion of the column address unit 13(FIG. 1) is depicted in greater detail in FIG. 5. A row of pixels of thedisplay is refreshed from data fed from the data processor 10 (FIG. 1)into a 2-bit m-stage shift register 50 (FIG. 5), where m is the numberof pixels in each row. The two bits of the p^(th) stage of the shiftregister characterise whether the p^(th) pixel is scheduled forswitching to the data `1` state from the data `0` state, for switchingto the data `0` state from the data `1` state, or for retaining thepixel in its pre-existing state, whether that was data `0` or data `1`.

Associated with each stage of the shift register 50 is a pair of latches51a and 51b respectively coupled with the first and second bits of thatstage of the shift register 50. Under the control of a clock pulseapplied to latch line 52, the data is entered from the shift register 50into the latches 51 where it is employed by logic units 53 to enable theappropriate one of three gates 54, 55 and 56 so as to connect the pixelcolumn electrode 32 either to rail 58 maintained at the potential of thefront-plane electrode or to rail 57 or 59, respectively maintained atpotentials equal amounts positive and negative with respect to thefront-plane potential.

In this way the processor 10 sets up a refresh row of data for thepixels of the cell 16 in the shift register 50 of the column addressunit 13, and the latches 51 employ the data, through the agency of thelogic units 53 and the sets of gates 54, 55 and 56, to set up therequisite potentials on column electrodes 32 for entry of that row.Selection of the appropriate pixel row of the cell 16 into which thedata is to be entered is under the control of the row addressing unit12, a portion of which is shown in greater detail in FIG. 6.

The pixels of cell 16 are arranged in n rows, and so the row addressunit has 2n decoder trees arranged in pairs so that there is a pair ofdecoder trees 60 and 61 associated with each row. The output of decodertree 60 of the r^(th) row of pixels is connected via a delay unit 62 torow electrode 31 of that row. Associated with each pair of decoder treesis an RS flip-flop 63 whose set and reset inputs are connected to theoutputs of decoder trees 60 and 61 respectively. The output of theflip-flop 63 is connected to the row electrode 41 of that row. In thequiescent state of the two decoder trees of that pixel row in which therow is not being addressed, the output of decoder tree 60 is such as tohold the row electrode 31 of that row at a potential which maintains thegates 30 in their disabled states. Additionally, in this condition, theoutput of the flip-flop 63 is such as to hold the row electrode 41 ofthat row at a potential which maintains the gates 40 in their enabledstates. Thus, in this condition, all the pixel pads 25 of the row aremaintained via column electrodes 42 at the potential of the front-planeelectrode 24.

The sequence of events involved in the refreshing of this row of pixelsis that the data processor 10 directs a signal to the decoder trees toaddress decoder tree 60 of the r^(th) row. This causes the decoder tree60 to set the flip-flop 63, thereby causing the disablement of the gates40 of that row and thus the electrical isolation of the pixel pads 25.The delay unit 62, which may for instance be constituted by a seriesconnected pair of inverters, ensures that this isolation occurs beforethe signal from decoder tree 60 is able to propagate through the delayunit and cause the enablement of the gates 30 of the row. Enablement ofthese gates 30 causes the pixel pads 25 to be charged to the selectedrail potential of the rails 57, 58 and 59 in accordance with the data atthat time held in the latches 51. The signal applied to the decoder tree60 from the data processor 10 is maintained for a sufficient time forthese pixel pads to charge up to the row potentials before being removedand thus cause the associated gates 30 to be restored to their disabledstates. At this stage the potentials developed across the pixels of theaddressed row have not been maintained long enough to cause the pixelsscheduled for switching yet to have become fully switched, but the dataprocessor is now able to proceed with setting a fresh row of data of adifferent row into the column addressing unit 13, and to start thesequence in the row addressing unit 12 for the entry of the data intothat different row into the cell 16. When sufficient time has elapsedfor the pixels to have become fully switched, the data processor 10directs another signal to the decoder trees to address decoder tree 61of the r^(th) row to cause it to reset the flip-flop 63. This causes theenablement of the gates of 40 of the r^(th) row, and thus the dischargeof the potentials held on the pixel pads of that row.

In this way the cell 16 can be refreshed with new rows of data using arow address time, t_(A), which can be considerably shorter than thetime, t_(S), for which a potential difference has to be maintainedacross any given pixel to cause it to switch from one of its bistablestates to the other. The durations t_(A) and t_(S) are regulated by thedata processor 10, and hence can be arranged to be controlled bysoftware so as to give the facility for easy adjustment. Alternatively,if the durations do not require changing, they can be determined byhardware, for instance by monostables. Under these circumstances thereneed be only one decoder tree per row, decoder tree 60. When a decodertree 60 is addressed by the data processor 10 it sets first and secondmonostables (not shown). The first monostable is connected to reset thedecoder 60 after a fixed duration t_(A), while the second monostable isconnected to reset the flip-flop 63 after a duration t_(S). Typicallythe duration t_(S) will be at the very least more than twice theduration t_(A), and may be much more than ten times.

In the foregoing description it has been tacitly assumed that thefront-plane electrode is at all times maintained at a constantpotential. If the construction of the back-plane sheet 23 is such thatit is able to drive the pixel pads 25 within the voltage range from 0volts to V volts then, if the front-plane electrode is to be maintainedat a fixed potential, this fixed potential is preferably V/2. Thisallows a maximum potential difference of +V/2 or -V/2 to be developedacross any pixel. This value can be increased to a potential differenceof +V or -V by arranging to alternate the potential of the front-planeelectrode between O and V, but under these circumstances a pair ofrefreshings of a row of pixels is required in order to provide acomplete refreshment because an individual refreshing is capable ofswitching pixels in one direction only. One refreshing of the pair ofrefreshings is with the front-plane electrode maintained at 0 volts, andthe other is with the front-plane electrode maintained at V volts.

With the fixed front-plane potential arrangement, the three rails 57, 58and 59 are respectively maintained at 0 volts, V/2 volts and V volts,but with an alternatively front-plane potential arrangement only rails57 and 59, as before respectively maintained at 0 volts and V volts, arerequired.

When the front-plane electrode is maintained at 0 volts, a potentialdifference of +V can be developed across a pixel by raising thepotential of its pixel pad 25 to V volts. Arbitrarily designating thetransition that such a potential difference induces as the data `0` todata `1` transition, it follows that, while the front-plane electrode ismaintained at 0 volts, it is possible to induce data `0` to data `1`transitions, but not possible to induce data `1` to data `0`transitions. The latter require the development of a potentialdifference of -V. Accordingly, while the front-plane electrode potentialis maintained at 0 volts, those pixels of a row being refreshed that arescheduled for making the data `1` to data `0` transition are treated inthe same way by the column address unit 13 as those pixels of the rowscheduled for being retained in their pre-existing states, that is tosay their column electrodes 32 are connected to the rail that ismaintained at the currently maintained potential of front-planeelectrode, namely rail 57. Then, while all gates 30 are disabled and allgates 40 are enabled, the potential of the front-plane electrode 24, israised together with that of the column electrodes 42, from 0 volts to Vvolts preparatory for the second of the pair of refreshings of this row.With the front-plane electrode row at V volts, it is possible to developa potential difference of -V across a pixel, but not a potentialdifference of +V. Accordingly those pixels that were scheduled formaking the data `0` to data `1 ` transition in the first refreshing ofthis pair of refreshings, and indeed made that transition, are nowtreated in the same way as those pixels scheduled for making neithertransition in this pair of refreshings, that is to say their columnelectrodes 44 are connected to the rail that is maintained at thecurrently maintained potential of the front-plane electrode, namely rail59.

It thus becomes clear that the column electrodes of pixels not scheduledto make either transition in either of the pair of refreshings need tobe connected to rail 57 during the first refreshing, and to rail 59during the second refreshing. This means that either the logic units 53must include inputs that characterise the front-plane electrodepotential, or that the data in the shift register 50 has to be rewrittenbetween the first and the second pair of addressings. If the latterapproach is adopted, each stage of the shift register 50 is required tocontain only one bit of information rather than two, namely anindication as to whether or not the associated pixel is scheduled formaking the data state transition that is possible with this particularrefreshing. The shift register can thus be a one-bit m-stage registerrather than a two-bit one.

One particular application for these back-plane co-ordinate addressedliquid crystal devices is as the active element of a matrix vectormultiplier, for instance for use as an optical cross-bar switch. In sucha matrix vector multiplier a columnar array of n optical sources isoptically arranged relative to the pixels of the co-ordinate array ofthe cell so that the p^(th) element of the column of sources isoptically coupled with all m pixels of the p^(th) row of the co-ordinatearray, while similarly a row array of m optical detectors is opticallyarranged relative to the pixels so that all n pixels of the r^(th)column of the co-ordinate array are optically coupled with the r^(th)element of the row of detectors. Conveniently a polarisation beamsplitter is employed in the optical coupling of the sources anddetectors with the co-ordinate array in order to provide the dualfunction of separating the input and output beams and of providing thenecessary polariser for operation of the device.

We claim:
 1. A method of addressing a liquid crystal cell having aco-ordinate array of pixels, wherein data for refreshing the cell iscompared with the data existing prior to refresh to determine thosepixels which require to have their states changed, and wherein thosepixels are accessed by developing a positive, or negative, electricpotential difference across those pixels, according into which statethey are to be changed, for a predetermined period of time beforere-establishing a zero potential difference, whereby no pixel isconsecutively accessed twice by the same polarity of potentialdifference.
 2. A method as claimed in claim 1, wherein, the modulus ofthe potential difference applied across a pixel to charge it from onestate to another is matched by the modulus of the potential differenceapplied across that pixel to change it from the other state to that one,and wherein the duration of potential difference application forswitching it from one state to the other is matched by the duration forswitching it from the other state to that one.
 3. A method ofco-ordinate addressing a liquid crystal cell that includes crystal layerwhich, by the application of oppositely directed electric potentialdifferences across the thickness of the layer, is enabled to be switchedbetween two stable states, which cell is switchable between said twostable states using an active back-plane provided with a co-ordinatearray of electrode pads on one side of the liquid crystal layer, whichpads co-operate with a front-plane electrode on the other side of theliquid crystal layer to define an associated co-ordinate array of pixelswithin the liquid crystal layer, wherein data for refreshing the cell iscompared, pixel address by pixel address, with preexisting datacurrently displayed by the pixels to determine which pixels require tohave their states changed, and wherein only those electrode pads whoseassociated pixels are pixels that require to have their states changedare accessed taking their potential from a potential equal to that ofthe front-plane electrode to a different potential for a predeterminedperiod before restoring to its former potential equal to that of thefront-plane electrode, the different potential being either apredetermined amount above the potential of the front-plane electrode,or an equal amount below that potential.
 4. A method as claimed in claim3, wherein, in the addressing of a pixel to switch it from either one ofthe two states to the other, its associated electrode pad is charged toa potential different from that of the front-plane electrode byconnection to a voltage source for a first duration, which connection isremoved to leave the pad electrically isolated at said differentpotential for the second duration, after which the pad is discharged tothe potential of the front-plane electrode.
 5. A method as claimed inclaim 4, wherein said second duration is at least as great as said firstduration.
 6. A method as claimed in claim 3, wherein the potential ofthe front-plane electrode is alternated between first and second levels,being maintained at the first level for the switching of pixels from aselected one of the two stable states to the non-selected state, andbeing maintained at the second level for the switching of pixels fromthe non-selected state to the selected state.
 7. A method as claimed inclaim 6, wherein, in the addressing of a pixel to switch it from eitherone of the two states to the other, its associated electrode pad ischarged to a potential different from that of the front-plane electrodeby connection to a voltage source for a first duration, which connectionis removed to leave the pad electrically isolated at said differentpotential for the second duration, after which the pad is discharged tothe potential of the front-plane electrode.
 8. A back-plane co-ordinateaddressed liquid crystal device, which device includes a liquid crystalcell containing a liquid crystal layer switchable, by the application ofoppositely directed electric potential differences across the thicknessof the layer, between two stable states, which cell has an activeback-plane provided with a co-ordinate array of electrode pads on oneside of the liquid crystal layer, which pads co-operate with afront-plane electrode on the other side of the liquid crystal layer todefine an associated co-ordinate array of pixels within the liquidcrystal layer, which device also includes a data processor which isadapted to compare data for refreshing the cell pixel address by pixeladdress with pre-existing data currently displayed by the pixels todetermine which pixels require to have their states changed, and isadapted to refresh the cell by taking the potential, only of thoseelectrode pads whose associated pixels are pixels that require to havetheir states changed, from a potential equal to that of the front-planeelectrode to a different potential for a predetermined period beforerestoring it to its former potential equal to that of the front-planeelectrode, the different potential being either a predetermined amountabove the potential of the front-plane electrode, or an equal amountbelow that potential.
 9. A back-plane co-ordinate addressed liquidcrystal device as claimed in claim 8, wherein each electrode pad isconnected by way of a first gated electrical path to a source ofpotential maintained at the potential of the front-plane electrode, andby way of a second stated electrical path to one of three sources ofpotential, one maintained at the potential of the front-plane electrodeand the other two maintained at potentials equally above and below thefront-plane electrode potential.
 10. A back-plane coordinate addressedliquid crystal device as claimed in claim 8, wherein each electrode padis connected by way of a first gated electrical path to a source ofpotential maintained at the potential of the front-plane electrode, andby way of a second gated electrode path to one of two sources ofpotential, one maintained at the potential of the front-plane potentialand the other to a potential alternately maintained at potentialsequally above and below the front-plane electrode potential.
 11. Amatrix vector multiplier incorporating a back-plane co-ordinateaddressed liquid crystal device, which device includes a liquid crystalcell containing a liquid crystal layer switchable, by the application ofoppositely directed electric potential differences across the thicknessof the layer, between two stables states, which cell has an activeback-plane provided with a co-ordinate array of electrode pads on oneside of the liquid crystal layer, which pads co-operate with afront-plane electrode on the other side of the liquid crystal layer todefine an associated co-ordinate array of pixels within the liquidcrystal layer, which device also includes a data processor which isadapted to compare data for refreshing the cell pixel address by pixeladdress with pre-existing data currently displayed by the pixels todetermine which pixels require to have their states changed, and isadapted to refresh the cell by taking the potential, only of thoseelectrode pads whose associated pixels are pixels that require to havetheir states changed, from a potential equal to that of the front-planeelectrode to a different potential for a predetermined period beforerestoring it to its former potential equal to that of the front-planeelectrode, the different potential being either a predetermined amountabove the potential of the front-plane electrode, or an equal amountbelow that potential.
 12. A matrix vector multiplier as claimed in claim11, wherein each electrode pad is connected by way of a first gatedelectrical path to a source of potential maintained at the potential ofthe front-plane electrode, and by way of a second stated electrical pathto one of three sources of potential, one maintained at the potential ofthe front-plane electrode and the other two maintained at potentialsequally above and below the front-plane electrode potential.
 13. Amatrix vector multiplier as claimed in claim 11, wherein each electrodepad is connected by way of a first gated electrical path to a source ofpotential maintained at the potential of the front-plane electrode, andby way of a second gated electrode path to one of two sources ofpotential, one maintained at the potential of the front-plane potentialand the other to a potential alternately maintained at potentialsequally above and below the front-plane electrode potential.